Device having a redundant structure

ABSTRACT

Device with a damascene interconnect for integrated circuits with improved reliability and improved electromigration properties. The device including a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a divisional of U.S. patent application Ser.No. 11/164,223 filed Nov. 15, 2005, the disclosure of which is expresslyincorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present invention relates to an interconnect structure, e.g., adamascene interconnect, for integrated circuits with improvedreliability and improved electromigration properties.

BACKGROUND DESCRIPTION

According to the known art, “fatwire” structure is a wiring layout laidout with a metal line having thicker height and wider width, e.g.,thickness and pitch of 2×, 4×, 6×, etc. of a thin wire, minimum groundrules dimensions. However, with regard to electromigration effects,reliability of fatwire structures with a larger pitch becomes worse thanin a thin wire structure. This inconsistent reliability is due to thefatwire structure. In this regard, fatwire failure generally occurs atthe top of the metal line, i.e., near the surface of the stripe, and/orat the bottom of the interlevel via. In the known structure, the bottomof the via may not fully contact the sidewall liner. Moreover, even whenthe via contacts the sidewall liner, the liner is too thin to sustainall the current density of the fatwire.

A conventional process for forming a dual damascene line is shown inFIGS. 1-4. In particular, a trench 12 is formed in a substrate 11 intowhich a metal, e.g., copper or aluminum, is provided, e.g., viaelectroplating, in order to form metal line Mx and at least one via Vx.Substrate 11 may be, e.g., Si0₂, a low K organic material, a PCVD lowdielectric material or other suitable material having a thickness of 400to 2500 angstroms, metal line Mx may have a thickness in a range between0.4-1.0 micron and a width of 0.2 to 1.0 micron, and via Vx may have adepth of 0.4 to 1.0 micron from the bottom of Mx and a diameter of 0.2to 0.4 micron. Moreover, substrate 11 may optionally be covered by ahardmask layer 13, which can be, e.g., a PCVD oxide, SiCNH, SiC, Si₃N₄,or other suitable material. Moreover, the portion of hardmask 13 overtrench 12 removed during the formation of trench 12 is filled with metalMx. Further, metal line Mx is patterned by removing excess metal fromthe upper surface of substrate 11 or optional hardmask 13, e.g., throughchemical mechanical polishing, to form a smooth upper surface.

In a next production step, a cap layer 14 is applied over the top ofsubstrate 11/hardmask 13 and metal line Mx. Cap layer 14 can be, e.g.,SiN_(x), SiCNH, or other suitable cap layer material for metal line Mx,and have a thickness of 200-1000 angstroms. A substrate or interlevellayer 15 is deposited onto cap layer 14. Interlayer 15, like substrate11, can be, e.g., Si0₂, a low K organic material, a PCVD lowk-dielectric material or other suitable material having a thickness of4000 (1×) to 24000 (6×). Optionally, a hardmask layer 16 can bedeposited onto the surface of interlevel layer 15. Hardmask layer 16 canbe, e.g., a PCVD oxide, SiCNH, or other suitable material with athickness of 300-2000 angstroms.

In a next step in the conventional process, as shown in FIG. 2, a dualdamascene trench 17 is formed in interlevel layer 15 and optionalhardmask 16. Trench 17, which is formed by, e.g., lithography andetching, is composed of two portions: a first portion 18 extending to adepth of 0.6-2 micron from the surface of interlevel layer 15/hardmask16 and a second portion 19 extending from first portion 18 down throughcap layer 14 to contact metal line Mx.

As illustrated in FIG. 3, a liner 20 is deposited into trench 17 inorder to form a barrier layer having a thickness of 50-500 angstroms.Liner 20 can be, e.g., Ta, TaN, W, Ti, TiN, or a combination of Ta, TaN,Ti, TiN, W or with other suitable material to act as a barrier layer forthe metal to be deposited in liner 20. Moreover, liner 20 can be formedfrom one or more of the identified materials.

As noted above, and shown in FIG. 4, a metal, e.g., copper, is depositedin trench 17, and more particularly liner 20, in order to form metalline MQ in portion 18 of trench 17 and via VL in portion 19 of trench17. Further, in accordance with the conventional process, wiring linesare patterned by removing excess metal from metal line MQ from the uppersurface of substrate 15 or optional hardmask 16, e.g., through chemicalmechanical polishing, to achieve a smooth upper surface with a metalstripe.

SUMMARY OF THE INVENTION

The present invention is directed to a method of fabricating a device.The method includes forming a trench in a metal stripe of a dualdamascene line, depositing a barrier layer in the trench, and filling aremainder of the trench with metal.

Moreover, the present invention is directed to a device that includes adual damascene line having a metal line and a via, and a redundant linerarranged to divide the metal line.

The instant invention is directed to a method for fabricating aninterconnect structure. The method includes forming a trench in asubstrate, depositing metal in the trench, forming a second trench inthe metal, depositing a redundant liner in the second trench, anddepositing metal in the second trench.

Still further, the invention is directed to a method of forming aredundant device that includes forming a redundant liner to divide ametal line of dual damascene line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 illustrate a conventional formation of a dual damascene line(prior arts); and

FIGS. 5-10 illustrate the formation of a redundant fatwire from theconventional dual damascene line depicted in FIG. 4 in accordance withthe features of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE PRESENT INVENTION

The invention relates to a process for forming a wire from aconventional dual damascene line. According to the invention, the formedfatwire eliminates the line opens and improves reliability(electromigration) by providing a longer lifetime and tighter sigma thanconventional fatwire structures.

According to the invention, the fatwire structure includes a thinredundant liner in the fatwire interconnect structure to isolate voidsfrom underneath the via and to prevent such voids from propagatingupward above the redundant liner. As a result, upward propagation ofvoids into the upper part of the metal layer is prevented.

The via opening is etched through the redundant liner, which increasesthe mechanical strength of the interconnect and essentially eliminatesany thermal cycle and/or stress migration effects. Further, the depth ofthe via improves performance against the electromigration effects byincreasing contact surface around the via.

The present invention increases the reliability of the conventional dualdamascene line shown in FIG. 4 by using a redundant line. In particular,as illustrated in FIG. 5, a blanket reactive ion etch (RIE) or a blanketwet etch is performed on the metal stripe, e.g., copper, to remove aportion of the thickness of metal line MQ to form metal line MQ′.However, the portion of barrier layer 20 lying adjacent the removedthickness is not removed, such that a trench 21 is formed between facingportions of barrier layer 20 and between an upper surface of metal lineMQ′ and the upper surface of interlevel layer 15/hardmask 16. Trench 21can be up to one-half of the thickness of metal line MQ, may be at least100 angstroms, and preferably, is between 10-30% of the thickness ofmetal line MQ.

After formation of trench 21, a barrier layer (redundant liner) 22, asshown in FIG. 6, is deposited onto the surface of interlevel layer15/hardmask 16, as well as into and along the sides of trench 21.Barrier layer 22 can have a thickness of 50-500 angstroms, preferably50-100 angstroms, and be formed of, e.g., Ta, TaN, W, Ti, TiN, or othersuitable material to act as a diffusion barrier layer for the metal tobe deposited in barrier layer 22. Moreover, layer 22 can be formed fromone or more of the identified materials. Thereafter, a metal, e.g.,copper, is deposited into trench 21, and more particularly into barrierlayer 22, in order to form metal line MQ″.

As shown in FIG. 7, a wiring line is patterned by removing excess metalfrom metal line MQ′ and portions of barrier layer 22 from the uppersurface of substrate 15 or optional hardmask 16, e.g., through chemicalmechanical polishing, to achieve a smooth upper surface with a metalstripe. Thus, barrier layer 22 forms a redundant layer in the middle ofthe fatwire, i.e., between metal lines MQ′ and MQ″.

In a next production step, as illustrated in FIG. 8, a cap layer 24 isapplied over the top of substrate 15/hardmask 16 and the metal stripepatterned from metal line MQ″. Cap layer 24 can be, e.g., SiNx, SiCNH,or other suitable cap layer material for metal line Mx, and have athickness of 200-1000 angstroms. A substrate or interlevel layer 25 isdeposited onto cap layer 24. Interlayer 25, like substrates 11 and 15,can be, e.g., Si0₂, a low K organic material, a PCVD low k-dielectricmaterial or other suitable material having a thickness of 5000 to 24000angstroms. Again, an optional hardmask layer (not shown) can bedeposited onto the surface of interlevel layer 25 in the manner setforth above.

As illustrated in FIG. 9, a trench 27 is formed in interlevel layer 25,e.g., by lithography and etching, and is composed of two portions: afirst portion 28 extending to a depth of 0.6-2 microns from the surfaceof interlevel layer 25 and a second portion 29 extending from firstportion 28 down through at least barrier (redundant) layer 22 in orderto create the desired redundance. Subsequently, a layer (liner) isdeposited into trench 27, followed by deposition of metal into trench27, or more specifically, into the liner within trench 27, in order toform metal line LN and via VQ, as shown in FIG. 10. Moreover, a portionof metal line LN can be etched so that a redundant liner can be placedwithin the etched portion, and then deposited with metal. The wiringline can be patterned by chemical mechanical polishing to provide asmooth surface and metal strip. This procedure can be repeated a numberof time, e.g., 8-9 times, depending upon the particular interconnectdesign.

In this manner, via VQ is etched through cap layer 24, barrier layer 22,and into MQ′. Thus, via VQ can be, e.g., a depth deeper than one-halfthe thickness of the fatwire. Moreover, barrier layer 22 additionallyforms a redundant layer between metal lines MQ′ and LN.

As a result of this construction, barrier layer 22 will prevent anyvoids from underneath via VQ from propagating upward to metal line MQ″.Further, the depth of via VQ will improve performance by increasing thecontact surface around via V2, and improve reliability by having alonger lifetime and tighter sigma. This type of interconnect, in whichthe via VQ is deep into the fatwire will make the structure mechanicallystronger, and, therefore, less prone to thermal cycle or stressmigration failures due to the expansion or contraction of metal and theinterlevel low k-dielectrics.

The circuit as described above is part of the design for an integratedcircuit chip. The chip design is created in a graphical computerprogramming language, and stored in a computer storage medium (such as adisk, tape, physical hard drive, or virtual hard drive such as in astorage access network). If the designer does not fabricate chips or thephotolithographic masks used to fabricate chips, the designer transmitsthe resulting design by physical means (e.g., by providing a copy of thestorage medium storing the design) or electronically (e.g., through theInternet) to such entities, directly or indirectly. The stored design isthen converted into the appropriate format (e.g., GDSII) for thefabrication of photolithographic masks, which typically include multiplecopies of the chip design in question that are to be formed on a wafer.The photolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

Moreover, the above-described method is used in the fabrication ofintegrated circuit chips.

While the invention has been described in terms of exemplaryembodiments, those skilled in the art will recognize that the inventioncan be practiced with modifications and in the spirit and scope of theappended claims.

1. A device comprising: a dual damascene line comprising a metal lineand a via; and a redundant liner arranged to divide the metal line. 2.The device in accordance with claim 1, further comprising: an interlevellayer formed over the dual damascene line; and the interlevel layercomprising at least one second metal line and at least one second via,the at least one second via extending through the redundant liner. 3.The device in accordance with claim 2, wherein the at least one secondvia extends into the metal line arranged below the redundant liner. 4.The device in accordance with claim 2, further comprising a cap layerformed between the dual damascene line and the interlevel layer.
 5. Thedevice in accordance with claim 1, further comprising: a plurality ofinterlevel layers formed over the dual damascene layer, wherein eachinterlevel layer includes at least one metal line divided by a redundantliner and at least via; and each at least one via extends through astructurally lower redundant liner.
 6. The device in accordance withclaim 5, further comprising a plurality of cap layers formed betweeneach of the plurality of interlevel layers.
 7. The device in accordancewith claim 1, further comprising at least one hardmask formed on atleast one of the plurality of interlevel layers.
 8. A device,comprising: a redundant liner structured and arranged to divide a metalline of dual damascene line; and a trench having at least a portionarranged to extend through the redundant liner.